Recently it is proposed to mount a plurality of memory chips of the same specifications in one package and use the plural memory chips respectively for a plurality of channels.
This technique can realize high integration, downsizing, etc.
Related references are as follows:    Japanese Laid-open Patent Publication No. 2006-251876;    Japanese Laid-open Patent Publication No. 2006-164323;    Japanese Laid-open Patent Publication No. 2003-45179; and    Japanese Laid-open Patent Publication No. 2007-108996.